This invention relates to programmable logic, and in particular to a high speed programmable logic device architecture employing BiCMOS repeater circuits in the interconnection array.
A programmable logic device (PLD) is a programmable integrated circuit that allows the user of the circuit to customize the logic functions the circuit will perform. The logic functions previously performed by small, medium and large scale integration integrated circuits are now capable of being performed by programmable logic devices. PLDs now have a capacity on the order of 50,000 gates per integrated circuit. When a typical programmable logic device is supplied by an integrated circuit manufacturer, it is not yet capable of performing any specific function. The user can program the PLD to perform the specific function or functions required by the user's application. The PLD then can function in a larger system designed by the user, just as though dedicated logic chips were employed. This functionality allows the user to debug the system logic without committing the time or expense of custom chips or gate arrays. It also allows small production runs, and the customization of hardware to suit a very specific application. In some PLD's the logic can be changed "on-the-fly" enabling the PLD to perform one function at one time during system operation, and another function at a later time.
A typical PLD consists of an array of identical logic cells that can be individually programmed and arbitrarily interconnected to each other to provide internal input and output signals, thus permitting the performance of highly complex combinational and sequential logic functions. The program is implemented in the PLD by setting the states of programmable elements such as memory cells.
Connections between logic cells, as well as between logic cells and the inputs and outputs of the PLD, are established via data buses that run throughout the PLD. For example, U.S. patent application Ser. No. 08/188,499 to Sasaki, also assigned to the Assignee of this application and incorporated here in its entirety by reference, discloses a grid-like bus structure where a set of horizontal bus lines transfers inputs to logic cells and a set of vertical bus lines accepts outputs from logic cells. To transfer data from one bus to another, some interconnection between buses must be established.
A possible means of interconnecting buses is a buffer or repeater circuit that will accept input data from one bus and supply that data to the other bus. Such a repeater circuit can also be equipped with a programmable enable input to control the operation of the repeater circuit.
A repeater can also be used to retransmit data along a bus to compensate for possible dissipation of the integrity of a data signal or noise as the signal travels along the length of the bus. For example, the repeater will boost a HIGH logic signal presented at its input to the original maximum level generated by the source of the signal so that at the final destination of the signal, whether it is another logic cell or a PLD output, a clean HIGH logic signal is received. A repeater circuit that transfers data along one bus, rather than from one bus to another, will be a bidirectional repeater, if data will be permitted to be transferred in either direction on the bus. Thus, the bidirectional repeater can be enabled to permit the transfer of data in either direction on a data bus.
In the prior art, it is known to construct repeaters in a PLD. For example, U.S. Pat. No. 4,317,557 to Carter discloses a CMOS buffer in a PLD. CMOS technology provides the benefit of reduced power consumption by the PLD, but does not provide the speed required for many applications. Bipolar technology, on the other hand, provides substantial speed benefits, but draws more power during circuit operation.
As PLDs are increasingly used in applications that require superior speed performance, it would be desirable to have a PLD with repeater circuits that can operate at high speeds but do not draw an excessive amount of power during circuit operation.